Motion estimation is employed to reduce temporal redundancy in digital video compression and is therefore a central part of the MPEG-x and the H.26x video coding standards. Conventional motion estimation computations command 60 to 80% of an encoding computational load. For large picture formats (i.e., standard definition and above) dedicated VLSI-architectures for motion estimation are employed. Numerous architectures exist for fixed block-size motion estimation (FBSME), which is based on a constant, translational motion model with fixed-size image blocks, usually 8 horizontal (H) by 8 vertical (V) or 16 H×16 V samples. A variable block size motion estimation (VBSME) processes, that allows a wider range of block sizes (i.e., 4 H×4 V, 4 H×8 V, 8 H×4 V, 8 H×8 V, 8 H×16 V, 16 H×8 V, and 16 H×16 V), provides better estimation of small and irregular motion fields resulting in a reduced number of bits used for coding prediction errors compared with FBSME. The VBSME process is a common component of motion models in recent video compression standards, such as H.264 and MPEG-4 Part 2, yet motion estimation processors that support VBSME are rare.
Two known VBSME approaches are currently available. A first VBSME approach uses a separate processing step for each block size. However, the first approach expends significant processing resources as a reference search area is traversed repeatedly, once for each block-size. A second VBSME approach operates on a smallest block-size and derives all larger block-size sum of absolute differences (SAD) by summing the corresponding small block-size SADs. Since the intermediate results from the small block-sizes are kept to generate the full block-size SADs, the second approach utilizes significant intermediate storage.